Add device tree bindings for the AMD-Xilinx Inter Processor Interrupts
(IPI) mailbox.

The IPI architecture allows the passing of messages across the system
without the complications of autonomous read-write transactions and
polling inefficiency. The notification of the interrupt is also
possible without message buffers on some platforms. Some IPI channels
are hard-wired to particular core while others can be configured to
assign to any core on AMD-Xilinx heterogenous multiprocessor platform.

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>

Add a new MBOX driver for the AMD-Xilinx IPI Mailbox, providing support
for the Versal-NET and Versal Gen 2 platforms

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>

Add the inter-processor interrupt (IPI) nodes to the device tree for the
Versal-NET platform, as per Versal-NET Technical Reference Manual (TRM).

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>

Add the inter-processor interrupt (IPI) nodes to the device tree for the
Versal Gen2 platform, as per Versal Gen2 Technical Ref Manual (AM026)

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>

Add support for testing AMD-Xilinx Inter-Processor-Interrupt(IPI) on
Versal-NET RPU.

Add an overlay configuration to assign IPI-5 as the default
inter-processor interrupt for RPU0 in Versal-NET. While IPI-5 is preset,
it can be adjusted based on design requirements.

rpu0_rpu0_mailbox is set up in loopback mode for testing.

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>

Add support for testing AMD-Xilinx Inter-Processor-Interrupt(IPI) on
Versal Gen2 RPU.

Add an overlay configuration to enable IPI-1 as the default
inter-processor interrupt for RPU0 in Versal Gen2. While IPI-1 is the
preset, it can be adjusted based on design requirements.

rpu0_rpu0_mailbox is set up in loopback mode for testing.

Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>